Microelectronic test structures


Nanodevice metrology


Variability and Mismatch


RF Measurements


Process Technology


Semiconductor Test and Measurements




 

March 24-27, 2014 Udine, Italy (website)


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Scope of the Conference


The 27th International Conference on Microelectronic Test Structures will be held in Udine, Italy, bringing together scientists, technicians, designers and users of characterization techniques and test structures to discuss recent developments and future directions. The conference will take place on March 25-27, 2014, preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 24.

A Best Paper award will be presented by the Technical Program Committee.

An Equipment exhibition relating to electronic devices measurements and characterization techniques will be held during the conference days. Vendors and manufacturers interested to participate can mail Dr. Alain Toffoli (Exhibition chair)

The conference will be technically sponsored by the IEEE Electron Devices Society.

A Special issue of IEEE Transactions on Semiconductor Manufacturing will publish a selection of the contributed papers.

Suggested topics  include, but are not limited to:

Characterization of new materials: Test structures and methods to evaluate new materials and devices, like graphene, CNTs. Test structure design methods: Design flows for automated design, verification strategies, design for analysis (methods to extract CA, number of squares, density, via/contact counts), parametrized design, design issues (grid, hierarchy, floating point issues, misalignment).

Replicated Feature Metrology: Level-to-Level registration, overlay, CD uniformity and control, non-electrical characterisation techniques, MOS effective gate length/width evaluation, mask and reticle process control.

Manufacturing of Integrated Circuits and MEMS: Evaluation of individual and groups of integrated circuit, device and MEMS process steps and elements: transistors, diodes, mechanical structures, device isolation, memory cells, and interconnect. Assessment of MMICs and RF components and products. Evaluation and optimisation of standard cell macros and other product circuits. Reliability and Product Failure Analysis: Test structures for quality assurance, transistor, thin film, dielectric and interconnect reliability, thermal monitoring and analysis, accelerated wafer level tests, wafer level burn-in, failure identification, reliability prediction.

Nanotechnology, Displays and Emerging Devices: Test structures and methods to evaluate nanotechnology (materials and devices), displays, optoelectronic materials and new devices. (BIO-)MEMS, (BIO-)Sensors and Actuators: Test structures for MEMS and micromachining including physical/chemical/optical sensors, photonic devices, image sensors and bio-sensors, amorphous silicon films and devices.

Device and Circuit Modelling, Parameter Extraction: Model parameter extraction, RF device modelling, de-embedding, pulsed measurements, DC and high frequency measurement techniques and applications.

Technology R&D and Integration: Test structures for FEOL or BEOL evaluation, design rule determination, process uniformity and worst-case analysis, test structures to assess integration and new technologies, multiplexed test chips/devices for large scale evaluations / reduced pad count.

Yield Enhancement, and Production Process Control: Yield enhancement structures and methods, critical area calculation, defect estimation structures and methods, yield modelling, evaluation of design-manufacturing interactions (Design for Yield), place and route methodology, Statistical Process Control. Large-scale, many-component test circuitry for technology assessment e.g. arrays, multiplexing techniques.

Test Structure Measurement Utilisation Strategy: Test equipment, probing and programmable testing for process diagnostics, optimizing test throughput, database and data analysis methods, statistical data analysis, expert systems and related techniques. Amongst others this includes capacitance, voltage, current, resistance, optical and thermal measurements. Matching and Variability Test Structures: Matching and variability of components (transistors, resistors, capacitors, inductors) layout for circuit applications and their evaluation. Characterisation of identically designed components. Matching models.




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Past Editions

 
2013 Osaka, Japan
2012 San Diego, USA
2011 Amsterdam, The Netherlands
2010 Hiroshima, Japan
2009 Oxnard, CA, USA
2008 Edinburgh, Scotland
2007 Tokyo, Japan
2006 Austin, Texas, USA
2005 Leuven, Belgium
2004 Hyogo, Japan
2003 Monterey, USA
2002 Cork, Ireland
2001 Kobe, Japan
2000 Monterey, USA
1999 Goteborg, Sweden
1998 Kanazawa, Japan
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1996 Trento, Italy
1995 Nara, Japan
1994 San Diego, USA
1993 Barcelona, Spain
1992 San Diego, USA
1991 Kyoto, Japan
1990 San Diego, USA
1989 Edinburgh, UK
1988 Long Beach, USA
1986 Long Beach, USA